The invention relates generally to digital logic. More particularly, the invention relates to a low power logic gate that is adaptable for use in memory address decoding.
Computing devices require memory. The memory can include read only memory (ROM) or random access memory (RAM). Generally, memory includes memory cells that are arranged in rows and columns. The individual memory cells are accessed through the use of row select lines and column select lines, typically referred to as word lines and bit lines.
Typically, a computing device accesses data stored in the memory cells of memory through address lines. Each memory cell has a particular address, which allows the computing device to access data stored within each memory cell.
An address decoder receives the address lines, and provides for selection of the proper word line and bit line based upon an address received by the address decoder. As previously described, the word lines and bit lines provide for selection of the memory cells.
ROM devices generally include an array of memory cells. The memory cells are typically configured in rows and columns. Each row generally includes a corresponding word line, and each column generally includes a corresponding bit line. FIG. 1 shows an ROM array of memory cells 110, 120, 130, 140, 150, 160, 170, 180, 190 and corresponding word lines (WL) and bit lines (BL). The ROM memory cells 110-190 are located at cross-points of the word lines and the bit lines, and each ROM memory cells 110-190 generally stores a bit of information.
The ROM memory cells 110-190 include functionality for setting the ROM memory cells 110-190 to one of at least two logical states. Each logical state represents a bit of information. Additionally, the ROM memory cells 110-190 include functionality for sensing the logical state of each of the ROM memory cells 110-190.
The logical state of a ROM cell can be set according to fuse, or anti-fuse ROM technology. A first state of a ROM cell can include a diode connection between the word line and the bit line selecting the ROM cell. A second state of a ROM cell can include an xe2x80x9copen circuitxe2x80x9d connection (that is, the lack of a connection) between the word line and the bit line selecting the ROM cell. Both of these states are generally easy to detect.
FIG. 2 shows logic gates included within a typical address decoder. The address decoder includes conventional diode-resistor logic (DRL) decoding. The decoder receives address lines A[0], A[1], A[2] and selects a corresponding word line WL1, WL2, WL3. Each word line includes a resistor 210, 211, 212 that is connected to a supply voltage potential. If any one of the address line inputs is at a low voltage potential, then the corresponding word line WL1, WL2, WL3 is pulled down to a low voltage potential (not selected) through the corresponding resistor 210, 211, 212, and a corresponding series diode. A word line is selected if all of corresponding address lines are at a high voltage potential, and the corresponding resistor 210, 211, 212 does not conduct current because none of the corresponding series diodes are conducting current.
Arrows 240, 250 depict current flow through the logic gates of non-selected word lines. It can be observed from FIG. 2 that the only pull up resistor 210, 211, 212 of the address decoder that does not conduct current is the pull up resistor 210 that corresponds to the selected word line. This can be problematic for large arrays of memory cells because large arrays of memory cells require many word lines. Since all of the word lines except the selected word line include a pull up resistor conducting current, a memory cell array including a large amount of word lines dissipates large amounts of power.
It is desirable to have an apparatus and method for a logic gate that consumes small amounts of power. It is desirable that the logic gate be adaptable for incorporation into memory address decoders. Particularly, memory address decoders of large memory arrays.
The invention includes an apparatus and method for a logic gate that consumes small amounts of power. The logic gate is adaptable for incorporation into memory address decoders.
A first embodiment of the invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential.
Another embodiment of the invention includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines. The plurality of address lines are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.